View TB6560FG_1187665.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TB6560HQ/FG
Preliminary
TOSHIBA BiCD Integrated Circuit
Silicon Monolithic
TB6560HQ,TB6560FG
PWM Chopper-Type bipolar Stepping Motor Driver IC
The TB6560HQ/FG is a PWM chopper-type sinusoidal micro-step bipolar stepping motor driver IC. It supports both 2-phase/1-2-phase/W1-2-phase/2W1-2-phase excitation mode and forward/reverse mode and is capable of low-vibration, high-performance drive of 2-phase bipolar type stepping motors using only a clock signal.
TB6560HQ
Features
* * * * * * * * * * * Single-chip bipolar sinusoidal micro-step stepping motor driver Uses high withstand voltage BiCD process: Ron (upper lower) = 0.6 (typ.) Forward and reverse rotation control available Selectable phase drive (2, 1-2, W1-2, and 2W1-2) High output withstand voltage: VCEO = 40 V High output current: IOUT = HQ: 3.5 A (peak) FG: 2.5 A (peak) Packages: HZIP25-P-1.27/HQFP64-P-1010-0.50 Built-in input pull-down resistor: 100 k (typ.) Output monitor pin equipped: MO current (IMO (max) = 1 mA) Equipped with reset and enable pins Built-in overheat protection circuit
TB6560FG
Weight: HZIP25-P-1.27: 9.86 g (typ.) HQFP64-P-1010-0.50: 0.26 g (typ.)
The TB6560HQ/FG is a Pb-free product. The following conditions apply to solderability: *Solderability 1. Use of Sn-63Pb solder bath *solder bath temperature = 230C *dipping time = 5 seconds *number of times = once *use of R-type flux 2. Use of Sn-3.0Ag-0.5Cu solder bath *solder bath temperature = 245C *dipping time = 5 seconds *the number of times = once *use of R-type flux *: Since this product has a MOS structure, it is sensitive to electrostatic discharge. These ICs are highly sensitive to electrostatic discharge. When handling them, please be careful of electrostatic discharge, temperature and humidity conditions.
1
2006-05-31
TB6560HQ/FG
Block Diagram
VDD 20/30, 31 M1 23/36
Protect 19/28
MO 17/23 Decoder
VMA 18/25, 26 OUT_AP 16/19, 20 Bridge driver A 13/10, 11
M2 22/35
CW/CCW 21/33
Overheat protection circuit
OUT_AM NFA
CLK
3/45 Input circuit
14/13, 14, 15
RESET 5/48
Current selector circuit A
+ 8/55, 56 VMB OUT_BP
ENABLE
4/47
DCY1 25/39 Decoder DCY2 24/38 Bridge driver B B
12/6, 7
9/61, 62 OSC 7/53 OSC Current selector circuit B Maximum current setting circuit 2/43 TQ1 1/42 TQ2 SGND PGNDA PGNDB 6/50, 51 15/16 10/1 + OUT_BM NFB
11/2, 3, 4
TB6560HQ/TB6560FG
2
2006-05-31
TB6560HQ/FG
Pin Functions
Pin No. HQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FG 42 43 45 47 48 50/51 53 55/56 61/62 1 2/3/4 6/7 10/11 13/14/15 16 19/20 23 25/26 28 30/31 33 35 36 38 39 I/O Input Input Input Input Input Input Output Output Output Output Output Input Output Input Input Input Input Input Input Symbol TQ2 TQ1 CLK ENABLE Functional Description Torque setting input (current setting) (built-in pull-down resistor) Torque setting input (current setting) (built-in pull-down resistor) Step transition, clock input (built-in pull-down resistor) H: Enable; L: All output OFF (built-in pull-down resistor) L: Reset (output is reset to its initial state) (built-in pull-down resistor) Signal ground (control side) Connects to and oscillates CR. Output chopping. Motor side power pin (B phase side) OUT_B output Power ground B channel output current detection pin (resistor connection). Short the two pins for FG. OUT_B output OUT_A output A channel output current detection pin (resistor connection). Short the two pins for FG. Power ground OUT_A output Motor side power pin (A phase side) When TSD, ON (open drain). Normal Z. Control side power pin. Forward/Reverse toggle pin. L: Forward; H: Reverse (built-in pull-down resistor) Excitation mode setting input (built-in pull-down resistor) Excitation mode setting input (built-in pull-down resistor) Current Decay mode setting input (built-in pull-down resistor) Current Decay mode setting input (built-in pull-down resistor) (Note 1) (Note 1) (Note 1) Initial state detection output. ON when in initial state (open drain). (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
RESET
SGND OSC VMB OUT_BM PGNDB NFB OUT_BP OUT_AM NFA PGNDA OUT_AP MO VMA Protect VDD CW/CCW M2 M1 DCY2 DCY1
HQ: No Non-connection (NC) FG: Other than the above pins, all are NC (Since NC pins are not connected to the internal circuit, a potential can be applied to those pins.) All control input pins: Pull-down resistor 100 k (typ.) Note 1: If the FG pin number column indicates more than one pin, the indicated pins should be tied to each other at a position as close to the pins as possible. (The electrical characteristics of the relevant pins in this document refer to those when they are handled in that way.)
Input pins (M1, M2, CLK, CW/CCW, ENABLE and RESET) VDD 100 100 100 k Output ins (MO, PROTECT)
3
2006-05-31
TB6560HQ/FG
Absolute Maximum Ratings (Ta = 25C)
Characteristic Power supply voltage HQ FG Symbol VDD VMA/B IO (PEAK) I (MO) VIN HQ Power dissipation FG Operating temperature Storage temperature Topr Tstg PD Rating 6 40 3.5 2.5 1 5.5 5 (Note 1) 43 (Note 2) 1.7 (Note 3) 4.2 (Note 4) -30 to 85 -55 to 150 C C W Unit V
Output current MO drain current Input voltage
Peak
A/phase mA V
Note 1: Ta = 25C, No heat sink. Note 2: Ta = 25C, with infinite heat sink (HZIP25). Note 3: Ta = 25C, with soldered leads. Note 4: Ta = 25C, when mounted on the board (4-layer board). Susceptible to the board layout and the mounting conditions.
Operating Range (Ta = -20 to 85C)
Characteristic Power supply voltage HQ FG Symbol VDD VMA/B IOUT VIN fCLK fOSC VMA/B > VDD = Test Condition Min 4.5 4.5 0 Typ. 5.0 Max 5.5 26.4 3 1.5 5.5 15 600 Unit V V A V kHz kHz
Output current Input voltage Clock frequency OSC frequency
4
2006-05-31
TB6560HQ/FG
Electrical Characteristics (Ta = 25C, VDD = 5 V, VM = 24 V)
Characteristic Input voltage Input hysteresis voltage High Low Symbol VIN (H) VIN (L) VH IIN (H) Test Circuit 1 1 M1, M2, CW/CCW, CLK, RESET , ENABLE, DECAY, TQ1, TQ2, ISD VIN = 5.0 V Built-in pull-down resistor Test Condition Min 2.0 M1, M2, CW/CCW, CLK, RESET , ENABLE, DECAY, TQ1, TQ2, ISD -0.2 Typ. 400 Max VDD 0.8 Unit V mV
Input current
1
30

55
80
A
IIN (L) IDD1
VIN = 0 V Output open, RESET : H, ENABLE: H (2, 1-2 phase excitation) 1 Output open, RESET : H, ENABLE: H (W1-2, 2W1-2 phase excitation) RESET : L, ENABLE: L
1 5
3
Consumption current VDD pin
IDD2 IDD3 IDD4
-5
3 2 2 0.5 0.7
5 5 5 1 2 5 30 55 80 100
mA
RESET : H, ENABLE: L
1
Consumption current VM pin Output channel margin of error
IM1 IM2
VO
RESET : H/L, ENABLE: L
RESET : H/L, ENABLE: H
B/A, COSC = 0.0033 F TQ1 = H, TQ2 = H
mA %
VNFHH VNF level Level differential VNFHL VNFLH VNFLL Minimum clock pulse width MO output residual voltage TSD TSD hysteresis Oscillating frequency tW (CLK) VOL MO TSD TSDhys fOSC

10 47 70
20 50 75
TQ1 = L, TQ2 = H TQ1 = H, TQ2 = L TQ1 = L, TQ2 = L
%

100
ns V C C kHz
IOL = 1 mA (Design target value) (Design target value) C = 330 pF
0.5

170 20 130
60
200
5
2006-05-31
TB6560HQ/FG
Electrical Characteristics (Ta = 25C, VDD = 5 V, VM = 24 V)
Output Block
Characteristic HQ Output ON resistor FG 2W1-2phase excitation 2W1-2phase excitation 2W1-2phase excitation 2W1-2phase excitation 2W1-2phase excitation 2W1-2phase excitation 2W1-2phase excitation 2W1-2phase excitation W1-2phase excitation
Symbol Ron U1H Ron L1H Ron U1F Ron L1F
Test Circuit
Test Condition IOUT = 1.5 A
Min

Typ. 0.3 0.3 0.35 0.35 100
Max 0.4 0.4 0.5 0.5
Unit
4 IOUT = 1.5 A
1-2phase excitation
=0
= 1/8
93
98
100
A-B chopping current (Note)
W1-2phase excitation
= 2/8
87
92
97
= 3/8
78 TQ1 = L, TQ2 = L 66
83
88 %
W1-2phase excitation
1-2phase excitation
Vector
= 4/8
71
76
= 5/8
51
56
61
W1-2phase excitation
= 6/8
33
38
43
= 7/8
15
20 100 500 0.1 0.1 0.1 0.3 0.2
25
2-phase excitation Reference voltage Output transistor switching characteristics VNF tr tf tpLH Delay time tpLH tpHL Output leakage current Upper side Lower side ILH ILL 6 7
TQ1, TQ2 = L (100%) OSC = 100 kHz RL = 2 , VNF = 0 V, CL = 15 pF
450

550

mV
RESET to output
ENABLE to output
s
VM = 40 V
1 1
A
Note: Maximum current ( = 0): 100%
6
2006-05-31
TB6560HQ/FG
Description of Functions
1. Excitation Settings
You can use the M1 and M2 pin settings to configure four different excitation settings. (The default is 2-phase excitation using the internal pull-down.)
Input M2 L L H H M1 L H L H Mode (Excitation) 2-phase 1-2-phase W1-2-phase 2W1-2-phase
2. Function
When the ENABLE signal goes Low level, it sets an OFF on the output. The output changes to the Initial mode shown in the table below when the RESET signal goes Low level. In this mode, the status of the CLK and CW/CCW pins are irrelevant.
Input CLK CW/CCW L H X X X X
RESET
H H L X
ENABLE H H H L CW
Output Mode
CCW Initial mode Z
X: Don't care
3. Initial Mode
When RESET is used, the phase currents are as follows. In this instance, the MO pin is L (connected to open drain).
Excitation Mode 2-phase 1-2-phase W1-2-phase 2W1-2-phase A Phase Current 100% 100% 100% 100% B Phase Current
-100%
0% 0% 0%
4. Current Decay Settings
Output is generated by four PWM blasts; 25% decay is created by inducing decay during the last blast in Fast mode; 50% decay is created by inducing decay during the last two blasts in Fast mode; and 100% decay is created by inducing all four blasts in Fast mode. If there is no input with the pull-down resistor connection then the setting is Normal.
Dcy2 L L H H Dcy1 L H L H Current Decay Setting Normal 0% 25% Decay 50% Decay 100% Decay
7
2006-05-31
TB6560HQ/FG
5. Torque Settings (Current Value)
The current ratio used in actual operations is determined in regard to the current setting due to resistance. Configure this for extremely low torque scenarios such as when Weak Excitation mode is stopped. If there is no input with the pull-down resistor connection then the setting is 100% torque.
TQ2 L L H H TQ1 L H L H Current Ratio 100% 75% 50% 20% (weak excitation)
6. Protect and MO (Output Pins)
You can configure settings from the receiving side by using an open-drain connection for the output pins and making the pull-up voltage variable. When a given pin is in its designated state it will go ON and output at Low level.
Pin State Low Z Protect Overheat protection operation Normal operation MO Initial state Other than initial state Open-drain connection
7. OSC
Output chopping waves are generated by connecting the condenser and having the CR oscillate. The values are as shown below (roughly: 30% margin of error).
Condenser 1000 pF 330 pF 100 pF Oscillating Frequency 44 kHz 130 kHz 400 kHz
8
2006-05-31
TB6560HQ/FG
Relationship between Enable, RESET and Output (OUT and MO)
Ex-1: ENABLE 1-2-Phase Excitation (M1: H, M2: L)
CW CLK ENABLE RESET MO (%) 100 71
IA
0
-71 -100
t0
t1
t2
t3
OFF
t7
t8
t9
t10
t11
t12
The ENABLE signal at Low level disables only the output signals. Internal logic functions proceed in accordance with input clock signals and without regard to the ENABLE signal. Therefore output current is initiated by the timing of the internal logic circuit after release of disable mode.
Ex-2: RESET 1-2-Phase Excitation (M1: H, M2: L)
CW CLK ENABLE
RESET
MO (%) 100 71
IA
0
-71 -100
t0
t1
t2
t3
t2
t3
t4
t5
t6
t7
t8
When the RESET signal goes Low level, output goes Initial state and the MO output goes Low level (Initial state: A Channel output current is 100%). Once the RESET signal returns to High level, output continues from the next state after Initial from the next raise in the Clock signal.
9
2006-05-31
TB6560HQ/FG
2-Phase Excitation (M1: L, M2: L, CW Mode)
CW CLK MO (%) 100 IA 0
-100
(%) 100 IB 0
-100
t0
t1
t2
t3
t4
t5
t6
t7
1-2-Phase Excitation (M1: H, M2: L, CW Mode)
CW CLK MO (%) 100 71 IA 0
-71 -100
(%) 100 71 IB 0
-71 -100
t0
t1
t2
t3
t4
t5
t6
t7
t8
10
2006-05-31
TB6560HQ/FG
W1-2-Phase Excitation (M1: L, M2: H, CW Mode)
CW CLK MO (%) 100 92 71
38
IA
0
-38
-71 -92 -100
(%) 100 92 71
38
IB
0
-38
-71 -92 -100
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
11
2006-05-31
TB6560HQ/FG
2W1-2-Phase Excitation (M1: H, M2: H, CW Mode)
CW CLK MO (%) 100 98 92 83 71 56 38 20 IA 0
-20 -38 -56 -71 -83 -92 -98 -100
(%) 100 98 92 83 71 56 38 20 IB 0
-20 -38 -56 -71 -83 -92 -98 -100
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32
12
2006-05-31
TB6560HQ/FG

CK
MO
M1 M2 RESET (%) 100 91 71.4 40
IA
0
-40 -71.4 -91 -100
1-2-phase excitation
W1-2-phase excitation
It is recommended that M1 and M2 signals be changed after setting the RESET signal Low during the Initial state (MO is Low). Even when the MO is Low, changing the RESET signal without setting the RESET signal Low may cause the discontinuity in the current waveform.
13
2006-05-31
TB6560HQ/FG
1. Current Waveform and Settings of Mixed Decay Mode
You can configure the points of the current's shaped width (current's pulsating flow) using 1-bit input in Decay mode for constant-current control. "NF" refers to the point at which the output current reaches its setting current value and "RNF" refers to the monitoring timing of the setting current. The smaller the MDT value, the smaller the current ripple (current wave peak), and the current's decay capability will fall.
fchop OSC Pin Internal Waveform Setting Current Value Normal Mode NF RNF
Charge mode NF: Setting current value reached Slow mode Current monitoring (When setting current value > Output current) Charge mode
Setting Current Value 25% Decay Mode NF
MDT Charge mode NF: Setting current value reached Slow mode Mixed decay timing Fast mode Current monitoring (When setting current value > Output current) Charge mode
RNF
Setting Current Value 50% Decay Mode NF
MDT Charge mode NF: Setting current value reached Slow mode Mixed decay timing Fast mode Current monitoring (When setting current value > Output current) Charge mode
RNF
Setting Current Value 100% Decay Mode NF
Charge mode NF: Setting current value reached Fast mode Current monitoring (When setting current value > Output current) Charge mode RNF
14
2006-05-31
TB6560HQ/FG
2. Current Control Modes (Decay Mode effect)
* Direction in which current value increases (sine wave)
Slow Setting Current Value Slow Fast Slow Charge
Fast Charge
Fast
Slow Setting Current Value Charge
Charge
Fast
*
Direction in which sine wave decreases (when a high decay ratio (MDT%) is used in Mixed Decay mode)
Slow Slow Charge Charge Since the current's rate of decay is fast, its compliance with the setting current value is also fast. Fast
Setting Current Value
Fast Slow Setting Current Value Slow
Fast
Charge
Fast
*
Direction in which sine wave decreases (when a low decay ratio (MDT%) is used in Mixed Decay mode)
Since the current's rate of decay is slow, its compliance with the setting current value takes a long time (or may not follow at all). Slow Slow Fast Charge Charge Fast
Setting Current Value
Slow Fast
Slow Fast
Setting Current Value
During Mixed Decay mode and Fast Decay mode, if the setting current value < output current at RNF: current monitoring point, the Charge mode at the next chopping cycle will disappear and the pattern will change to Slow Fast Mode (Slow Fast occurs at MDT). (In reality, a charge is applied momentarily to confirm the current.) Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show transient response curves.
15
2006-05-31
TB6560HQ/FG
3. Mixed Decay Mode Waveform (Current Waveform)
fchop OSC Pin Internal Waveform fchop
IOUT Setting Current Value 25% Mixed Decay Mode Setting Current Value NF
NF
RNF MDT (Mixed Decay Timing) Points
*
When the NF points come after mixed decay timing
Switches to Fast mode after Charge mode fchop fchop Setting current value MDT (Mixed Decay Timing) Points NF RNF NF
IOUT
Setting Current Value 25% Mixed Decay Mode
RNF
CLK Signal Input
*
When the output current value > Setting current value in mixed decay mode
fchop Setting Current Value IOUT NF
fchop
fchop
RNF Setting Current Value
NF
25% MIXED DECAY MODE
RNF
MDT (Mixed Decay Timing) Points
CLK Signal Input
*: Even if the output current rises above the setting current at the RNF point, a charge is applied momentarily to confirm the current.
16
2006-05-31
TB6560HQ/FG
4. Fast Decay Mode Waveform
After the current value set by RNF, torque or other means is attained, the output current to load will make the transition to full regenerative mode.
fchop Setting Current Value IOUT
Transition to Charge mode for a brief moment
Fast Decay Mode (100% Decay Mode)
RNF
Setting Current Value
NF
RNF Since the setting current value > output current, charge mode NF Fast Decay mode transition will take place at even the next cycle. RNF
CLK Signal Input
17
2006-05-31
TB6560HQ/FG
5. CLK Signal and Internal CR CK Output Current Waveform (when the CLK signal is input in the middle of Slow mode)
25% Mixed Decay Mode fchop fchop OSC Pin Internal Waveform Setting Current Value IOUT NF MDT fchop
NF Setting Current Value
RNF
MDT
RNF
CLK Signal Input The CR counter is reset here.
Transition to Charge mode for a brief moment
When the CLK signal is input, the Chopping Counter (OSC Counter) is forcibly reset at the timing of the OSC. As a result, the response to input data is fast in comparison to methods that don't reset the counter. The delay time is one OSC cycle: 10 s @100 kHz Chopping using the Logic Block logic value. After the OSC Counter is reset by CLK signal input, the transition is invariably made to Charge mode for a brief moment to compare the current. Note: Even in Fast Decay Mode, the transition is invariably made to Charge mode for a brief moment to compare the current.
18
2006-05-31
TB6560HQ/FG
6. CLK Signal and Internal OSC Output Current Waveform (when the CLK signal is input in the middle of Charge mode)
25% Mixed Decay Mode fchop fchop OSC Pin Internal Waveform fchop
Setting Current Value
MDT
NF Setting Current Value RNF MDT
IOUT
RNF
CLK Signal Input
Transition to Charge mode for a brief moment The OSC Counter is reset here.
19
2006-05-31
TB6560HQ/FG
7. CLK Signal AND Internal OSC Output Current Waveform (when the CLK signal is input in the middle of Fast mode)
25% Mixed Decay Mode fchop fchop OSC Pin Internal Waveform Setting Current Value IOUT NF fchop
MDT
Setting Current Value
NF MDT
RNF
RNF
CLK Signal Input
Transition to Charge mode for a brief moment The OSC Counter is reset here.
20
2006-05-31
TB6560HQ/FG
8. Internal OSC Output Current Waveform when Setting Current is Reverse (when the CLK signal is input using 2-phase excitation)
25% Mixed Decay Mode fchop fchop fchop
Setting Current Value IOUT
0
RNF Setting Current Value NF CLK Signal Input The OSC Counter is reset here. RNF
MDT
NF
21
2006-05-31
TB6560HQ/FG
Current Draw-out Path when ENABLE is Input in Mid Operation
When all the output transistors are forced OFF during Slow mode, the coil energy is drawn out in the following modes: Note: Parasitic diodes are indicated on the designed lines. However, these are not normally used in Mixed Decay mode.
VM VM VM
U1 ON Note
U2 OFF
U1 OFF Note
U2 OFF
U1 OFF Note
U2 OFF
Load OFF L1 ON L2 ON L1
Load
ENABLE is input L2 ON L1 OFF
Load L2 OFF
RNF PGND
RNF PGND
RNF PGND
Charge Mode
Slow Mode
Force OFF Mode
As shown in the figure above, an output transistor has parasitic diodes. Normally, when the energy of the coil is drawn out, each transistor is turned ON and the power flows in the opposite-to-normal direction; as a result, the parasitic diode is not used. However, when all the output transistors are forced OFF, the coil energy is drawn out via the parasitic diode.
22
2006-05-31
TB6560HQ/FG
Output Stage Transistor Operation Mode
VM VM VM
U1 ON Note
U2 OFF
U1 OFF Note
U2 OFF
U1 OFF Note
U2 ON
Load OFF L1 ON L2 ON L1
Load L2 ON L1 ON
Load L2 OFF
RNF PGND
RNF PGND
RNF PGND
Charge Mode
Slow Mode
Fast Mode
Output Stage Transistor Operation Functions
CLK CHARGE SLOW FAST U1 ON OFF OFF U2 OFF OFF ON L1 OFF ON ON L2 ON ON OFF
Note: The above chart shows an example of when the current flows as indicated by the arrows in the above figures. If the current flows in the opposite direction, refer to the following chart:
CLK CHARGE SLOW FAST U1 OFF OFF ON U2 ON OFF OFF L1 ON ON OFF L2 OFF ON ON
Upon transitions of above-mentioned functions, a dead time of about 300 ns is inserted respectively.
23
2006-05-31
TB6560HQ/FG
Measurement Waveform
CLK
tCLK
tCLK
tpLH VM 90% 50% 10% tr tf tpHL 90% 50% 10%
GND
Figure 1 Timing Waveforms and Names
OSC-Charge DELAY: The conversion from the OSC waveform to the internal OSC waveform is done by recognizing the level of chopping wave. The voltages of 2 V or above are considered as a High level, and voltages of 0.5 V or below are considered as a Low level as designed values. However, there is a response delay and that there occurs the peak-to-peak voltage variation.
2V OSC Waveform 0.5 V
OSC Pin Internal Waveform
Figure 2 Timing Waveforms and Names (CR and Output)
24
2006-05-31
TB6560HQ/FG
Power Dissipation
TB6560HQ
25
2006-05-31
TB6560HQ/FG
1. How to Turn on the Power
Turn on VDD. When the voltage has stabilized, turn on VMA/B. In addition, set the Control Input pins to Low when inputting the power. (All the Control Input pins are pulled down internally.) Once the power is on, the CLK signal is received and excitation advances when RESET goes high and excitation is output when ENABLE goes high. If only RESET goes high, excitation won't be output and only the internal counter will advance. Likewise, if only ENABLE goes high, excitation won't advance even if the CLK signal is input and it will remain in the initial state. The following is an example:
CLK
RESET
H L H L H L
ENABLE
OUT
Z
Output
Internal current Setting
Output current setting
Z Internal current setting: Invariable Output OFF Internal current setting: Variable
2. Calculating the Setting Current
To perform constant-current operations, it is necessary to configure the base current using an external resistor. If the voltage on the NFA (B) pin is 0.5 V (with a torque of 100%) or greater, it will not charge. Ex.: If the maximum current value is 1 A, the external resistance will be 0.5 W.
3. PWM Oscillator Frequency (External Condenser Setting)
An external condenser connected to the OSC pin is used to internally generate a saw tooth waveform. PWM is controlled using this frequency. Toshiba recommends 100 to 3300 pF for the capacitance, taking variations between ICs into consideration. Approximation: fosc = 1/(Cosc x 1.5 x (10/Cosc + 1)/66) x 1000 kHz
4. Power Dissipation
The IC power dissipation is determined by the following equation: P = VDD x IDD + IOUT x Ron x 2 drivers The higher the ambient temperature, the smaller the power dissipation. Check the PD-Ta curve, and be sure to design the heat dissipation with a sufficient margin.
5. Heat Sink Fin Processing
The IC fin (rear) is electrically connected to the rear of the chip. If current flows to the fin, the IC will malfunction. If there is any possibility of a voltage being generated between the IC GND and the fin, either ground the fin or insulate it.
26
2006-05-31
TB6560HQ/FG
6. Thermal Protection
When the temperature reaches 170C (as standard value), the thermal protection circuit is activated switching the output to off. There is a variation of plus or minus about 20C in the temperature that triggers the circuit operation.
27
2006-05-31
TB6560HQ/FG
5V
10 F
1 F
47 F
1 F
24 V
CLK
VDD
VMA
VMB OUTAP H-SW A OUTAM
RESET
ENABLE M1 M2 MCU or External input CW/CCW DCY1 DCY2 TQ1 TQ2 Protect MO R1 3.3 V or 5.0 V R2 OSC 100 pF 400 kHz - Current Control NFCompA Logic
OUTBP H-SW B OUTBM
M
NFA NFCompB RNFA
NFB RNFB SGND PGND 0.5 : IOUTmax = 1.0 A
28
2006-05-31
TB6560HQ/FG
Package Dimensions
Weight: 9.86 g (typ.)
29
2006-05-31
TB6560HQ/FG
Package Dimensions
Weight: 0.26 g (typ.) Note: The rear heat sink block will be 5.5 mm x 5.5 mm. (PROVISIONAL)
30
2006-05-31
TB6560HQ/FG
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice. 021023_D
060116EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
31
2006-05-31

▲Up To Search▲

Price & Availability of TB6560FG

	To Download TB6560FG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .